The present invention relates in general to substrate manufacturing technologies and in particular to methods for the optimization of substrate etching in a plasma processing system.
In the processing of a substrate, e.g., a semiconductor substrate or a glass panel such as one used in flat panel display manufacturing, plasma is often employed. As part of the processing of a substrate for example, the substrate is divided into a plurality of dies, or rectangular areas, each of which will become an integrated circuit. The substrate is then processed in a series of steps in which materials are selectively removed (etching) and deposited (deposition) in order to form electrical components thereon.
In an exemplary plasma process, a substrate is coated with a thin film of hardened emulsion (i.e., such as a photoresist mask) prior to etching. Areas of the hardened emulsion are then selectively removed, causing components of the underlying layer to become exposed. The substrate is then placed in a plasma processing chamber on a substrate support structure comprising a mono-polar or bi-polar electrode, called a chuck or pedestal. Appropriate etchant source are then flowed into the chamber and struck to form a plasma to etch exposed areas of the substrate.
Referring now to FIG. 1, a simplified diagram of plasma processing system components is shown. Generally, an appropriate set of gases is flowed into chamber 102 through an inlet 108 from gas distribution system 122. These plasma processing gases may be subsequently ionized to form a plasma 110, in order to process (e.g., etch or deposition) exposed areas of substrate 114, such as a semiconductor substrate or a glass pane, positioned with edge ring 115 on an electrostatic chuck 116. In addition, liner 117 provides a thermal barrier between the plasma and the plasma processing chamber, as well as helping to optimize plasma 110 on substrate 114.
Gas distribution system 122 is commonly comprised of compressed gas cylinders 124a–f containing plasma processing gases (e.g., C4F8, C4F6, CHF3, CH2F3, CF4, HBr, CH3F, C2F4, N2, O2, Ar, Xe, He, H2, NH3, SF6, BCl3, Cl2, WF6, etc.). Gas cylinders 124a–f may be further protected by an enclosure 128 that provides local exhaust ventilation. Mass flow controllers 126a–f are commonly a self-contained devices (consisting of a transducer, control valve, and control and signal-processing electronics) commonly used in the semiconductor industry to measure and regulate the mass flow of gas to the plasma processing system. Injector 109 introduces plasma processing gases 124 as an aerosol into chamber 102.
Induction coil 131 is separated from the plasma by a dielectric window 104, and generally induces a time-varying electric current in the plasma processing gases to create plasma 110. The window both protects induction coil from plasma 110, and allows the generated RF field to penetrate into the plasma processing chamber. Further coupled to induction coil 131 at leads 130a–b is matching network 132 that may be further coupled to RF generator 138. Matching network 132 attempts to match the impedance of RF generator 138, which typically operates at 13.56 MHz and 50 ohms, to that of the plasma 110.
Generally, some type of cooling system is coupled to the chuck in order to achieve thermal equilibrium once the plasma is ignited. The cooling system itself is usually comprised of a chiller that pumps a coolant through cavities in within the chuck, and helium gas pumped between the chuck and the substrate. In addition to removing the generated heat, the helium gas also allows the cooling system to rapidly control heat dissipation. That is, increasing helium pressure subsequently also increases the heat transfer rate. Most plasma processing systems are also controlled by sophisticated computers comprising operating software programs. In a typical operating environment, manufacturing process parameters (e.g., voltage, gas flow mix, gas flow rate, pressure, etc.) are generally configured for a particular plasma processing system and a specific recipe.
In a common substrate manufacturing method, known as dual damascene, dielectric layers are electrically connected by a conductive plug filling a via hole. Generally, an opening is formed in a dielectric layer, usually lined with a TaN or TiN barrier, and then subsequently filled with a conductive material (e.g., aluminum (Al), copper (Cu), etc.) that allows electrical contact between two sets of conductive patterns. This establishes electrical contact between two active regions on the substrate, such as a source/drain region. Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). A blanket layer of silicon nitride is then deposited to cap the copper.
There are generally three commonly used approaches for manufacturing dual damascene substrates: via-first, trench-first, and self-align. In one example of the via-first methodology, the substrate is first coated with photoresist and then the vias are lithographically patterned. Next, an anisotropic etch cuts through the surface cap material and etches down through the low-k layer of the substrate, and stops on a silicon nitride barrier, just above the underlying metal layer. Next, the via photoresist layer is stripped, and the trench photoresist is applied and lithographically patterned. Typically, some of the photoresist will remain in the bottom of the via, or the via may be covered by an organic ARC plug, in order to prevent the lower portion via from being over-etched during the trench etch process. A second anisotropic etch then cuts through the surface cap material and etches the low-k material down to a desired depth. This etch forms the trench. The photoresist is then stripped and the Silicon Nitride barrier at the bottom of the via is opened with a very soft, low-energy etch that will not cause the underlying copper to sputter into the via. As described above, the trench and via are filled with a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) and polished by chemical mechanical polishing (CMP). And although the via-first approach has been widely adopted for small geometry devices because of a large window for misalignment, it is also prone to photoresist poisoning and a crown like fence over the via.
An alternate methodology is trench-first. In one example of a dual hard mask approach, the substrate is coated with photoresist and a trench lithographic pattern is applied. An anisotropic dry etch then cuts through the surface hard mask (again typically SiN, TiN or TaN) followed by stripping the photoresist. Another photoresist is applied over the trench hard mask and then the vias are lithographically patterned. A second anisotropic etch then cuts through cap layer and partially etches down into the low-k material. This etch forms the partial vias. The photoresist is then stripped for trench etch over the vias with the hard mask. The trench etch then cuts through the cap layer and partially etches the low-k material down to desired depth. This etch also clears via holes at the same time stopping on the final barrier located at the bottom of the via. The bottom barrier is then opened with a special etch. However, trench-first methodology also requires near-perfect trench-to-via alignment in order to properly etch the via.
Yet another methodology is called self-align. This method combines the oxide etch steps but requires two separate ILD (interlevel dielectric) depositions with an intervening nitride mask and etch step. The lower (via) dielectric is deposited with a nitride etch stop on both top and bottom. The top nitride is masked and etched to form a via hard mask. This requires a special nitride etch process. Then the top (line) dielectric is deposited. Finally, the trench mask is aligned with the via openings that have been etched in the nitride, and both the trench and vias are etched in both layers of oxide with one etch step. However, the self-align methodology often requires high nitride-to-oxide etch selectivity and, like the trench-first methodology, requires near-perfect trench-to-via alignment in order to properly etch the via.
To facilitate discussion, FIG. 2A illustrates an idealized cross-sectional view of the layer stack, representing the layers of an exemplar semiconductor IC, prior to a lithographic step. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of the layer stack, there is shown a layer 208, comprising a semi-conductor, such as SiO2. Above layer 208 is disposed a barrier layer 204, typically comprising nitride or carbide (e.g., SiN, SiC, etc.). Dual damascene substrates further comprise a set of metal layers including M1 209a–b, typically comprising aluminum or copper. Above the barrier layer 204, is disposed a intermediate dielectric (IMD) layer 206, comprising a low-k material (e.g., SiOC, etc.). Above the IMD layer 206, there may be placed a cap layer 203, typically comprising SiO2. Above cap layer 203, there may be disposed a trench mask layer 202, typically comprising TiN, SiN, or TaN.
FIG. 2B shows a somewhat idealized cross-sectional view of the layer stack of FIG. 2A, after photoresist layer 220 and a BARC layer 222 is further added.
FIG. 2C shows a somewhat idealized cross-sectional view of the layer stack of FIG. 2B after photoresist layer 220 and BARC layer 222 have been processed through lithography. In this example, a photoresist mask pattern is created with a set of trenches 214a–b. 
FIG. 2D shows the cross-sectional view of the layer stack of FIG. 2C after trench mask layer 202 has been processed in the plasma system, further extending trench 214a–b to cap layer 203.
FIG. 2E shows the cross-sectional view of the layer stack of FIG. 2D, after photoresist layer 220 and a BARC layer 222 are removed.
FIG. 2F shows the cross-sectional view of the layer stack of FIG. 2E after a second photoresist layer 216 and a BARC layer 218 are disposed, in order to create a second metal layer and a via connecting it to the first metal layer 209a–b. 
FIG. 2G shows the cross-sectional view of the layer stack of FIG. 2F after the photoresist layer has been opened and an etch has been performed to partially etch into IMD layer 206 to create a via.
FIG. 2H shows the cross-sectional view of the layer stack of FIG. 2G after photoresist layer 216 and BARC layer 218 have been stripped, and an additional etch process has been performed to extend the trench to a desired depth and etch through a via stopping on barrier layer 204.
In FIG. 2I, the barrier layer 204 is etched through using, for example CH2F2, CH3F, etc. In FIG. 2J, a chemical mechanical polish process has been performed to polish the layer stack down to cap layer 203, and a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) has been deposited to contact the existing M1 metal material.
However, escalating requirements for high circuit density on substrates may be difficult to satisfy using current plasma processing technologies where sub-micron via contacts and trenches have high aspect ratios. The utilization of new low-k films and complex film stacks present a new set of challenges for dielectric etch processes and equipment.
For example, in these and other substrate manufacturing methods, the process of removing photoresist and BARC (bottom anti-reflective coating) can often damage low-k material in the substrate. Generally, low-k material consists of a large concentration of carbon and hydrogen, which helps to improve mechanical strength to current flow and minimizes cross talk between conductor lines. However, oxygen used in conventional photoresist stripping processes may react with the carbon in the photoresist to create volatile CO2 gas and substantially reduces the carbon concentration in exposed areas. Since, lowering carbon content may also substantially increase the corresponding k value, photoresist removal may detrimentally increase the RC time delay.
In addition, exposure to oxygen may aggravate via corner erosion and fencing, as well as cause trench and via dimensional changes. This may become even more problematic as substrate manufactures pursue next generation dielectrics with extremely low-k values (<2) and thus very high carbon concentrations. These materials, aside from potentially presenting substantial mechanical adhesion problems during CMP (chemical-mechanical polishing) processes, may also be susceptible to pitting and severe dimensional changes during processes that contain substantial amounts of oxygen, such as photoresist stripping. Referring now to FIG. 3A, the a cross-sectional view of a layer stack, as shown in FIG. 2, in which fencing 302 has occurred. Referring now to FIG. 3B, the a cross-sectional view of a layer stack, as shown in FIG. 2, in which corner erosion 304 has occurred.
In view of the foregoing, there are desired improved methods for the optimization of substrate etching in a plasma processing system.